The Josephson effect was discovered in 1962, and it soon found practical application as a research tool. The effect can, inter alia, also be used to make an extremely fast electronic switch, generally referred to as the Josephson junction. In addition to its sort switching time, the Josephson junction also has very low energy dissipation. Primarily because of these two characteristics, the Josephson junction can be used in devices or circuits, to be referred to as "Josephson devices", that are, inter alia, considered for use in future electronic computers. See, for instance, W. Anacker, IEEE Spectrum, May 1979, pp. 26-37, incorporated herein by reference, where the theory underlying the operation of Josephson junctions and devices is discussed, and junction parameters are defined. These aspects of Josephson device technology will therefore not be further discussed herein.
During a typical fabrication process for an (integrated) Josephson device more than a dozen different layers are usually deposited. However, the essential elements of a Josephson junction are a superconducting base electrode, a thin tunneling layer or barrier covering the base electrode in the junction region, and a superconducting counter electrode, overlying the tunnel layer. For a description of the structure and the fabrication process, see, for instance, J. H. Greiner et al, IBM Journal of Research and Development, Vol. 24(2), March 1980, pp. 195-205, incorporated herein by reference.
The base electrode material may be a Pb-In-Au alloy, and the counter electrode material a Pb-Bi alloy. A junction-defining thick dielectric layer between base and counter electrodes typically consists of vacuum-deposited SiO, and the tunnel layer typically is native oxide grown on the exposed base electrode surface prior to the deposition of the counter electrode material.
Formation of the tunnel barrier is probably the most critical step in the fabrication of Josephson devices, and has received a great deal of attention. Since the Josephson (pair) current and the single-electron (or quasi-particle) tunneling currents depend exponentially on the product of the tunneling barrier thickness and the square root of the barrier height times the effective mass of the tunneling particles, precise control of the tunnel barrier layer thickness and composition are required in order to achieve reproducible values of the tunneling current. For instance, for a typical tunnel barrier having a tickness of 4 nm, a thickness deviation of only 0.4 nm causes the value of the Josephson critical current, an important junction parameter, to vary by a factor of about 10.
The tunnel barrier is, for instance, formed by placing the bared junction region of the base electrode into a radio frequency glow discharge established in a low-pressure, pure-oxygen atmosphere in a vacuum chamber. Although this process permits relatively close control over barrier layer formation, there typically still exist substantial variations of device parameters, e.g., of the critical current, between devices fabricated on the same substrate wafer, as well as between devices on different wafers manufactured either during one and the same barrier layer formation run, or in different runs. However, for instance, for computer applications of Josephson devices, it is desirable, if not economically imperative, that many such devices, typically hundreds, perhaps thousands, be placed on the same substrate chip, and many chips be prepared simultaneously, and that these devices be closely matched in their properties. For instance, present design criteria typically call for the critical currents to be within 10 percent of the target value. Because such close intra- and inter-wafer (or chip) tolerances are difficult to achieve during the junction formation process, techniques for trimming or adjusting junction or device parameters subsequent to the formation of the junction on the device are being sought.
It has been shown that the critical current of Pb-Bi alloy junctions may be changed substantially "globally", i.e., essentially simultaneously in all, or at least a substantial fraction of all, junctions on a chip (or wafer), by annealing the chip (or wafer) at an elevated temperature (R. F. Broom et al, IBM Journal of Research and Development, Vol. 24(2), March 1980, pp. 206-211). Typical annealing temperatures and times were 80.degree. C. and one hour, respectively.
"Local" critical current adjustment, i.e., selective adjustment of individual junctions, has been accomplished by irradiating particular junctions with energetic electrons (&gt;5 keV, ibid). The observed changes in the critical current and the room temperature resistance of thus irradiated junctions were attributed to the creation of disorder in the barrier oxide layer by the energetic electrons. An increase in the critical current by 50 percent was reported for an electron dosage of 0.1 C/cm.sup.2 and an accelerating voltage of 30 kV.
Electron irradiation of lead-alloy Josephson junctions has also been reported by Y. H. Lee and P. R. Brosious, Applied Physics Letter, Vol. 40(4), 1982, pp. 347-349. These workers show that, under the conditions used by them, radiation-induced point defects within the tunnel barrier are responsible for the observed changes in both the tunneling current and the annealing characteristics of the junctions.
Prior art methods of altering Josephson junction parameters thus appear to achieve their end by means of altering the state of the barrier oxide, e.g., by means of annealing (which can be expected to result in relaxation of the barrier layer towards equilibrium), or by means of electron bombardment (which typically results in increased disorder in the barrier layer).
Because of the importance of the problem of excessive parameter scatter among Josephson devices on the same chip or wafer, or scatter from wafer to wafer, it is highly desirable to have a variety of trimming techniques available, such as to be able to choose the one suitable for a particular processing technique and/or particular device. Furthermore, it is desirable to have available a trimming technique that allows close control over the amount of resulting change in device parameter, that is fully compatible with current Josephson device manufacturing techniques, that does not adversely affect device stability, and that can easily be applied globally as well as locally. We will be disclosing such a technique below.